Jpn. J. Appl. Phys. 29 (1990) pp. 1377-1384  |Next Article|  |Table of Contents|
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New Package Cooling Technology Using Low Melting Point Alloys

Yoshitake Fukuoka and Masaru Ishizuka¹

(Received January 25, 1990; accepted for publication May 19, 1990)

This paper describes one of the new package cooling technology concepts using low melting point alloys in order to perform high density packaging. Two kinds of cooling alloy materials, Bi/Sn/In and Bi/Pb/Sn/In, whose melting points are less than 80°C and which are not expensive, were selected. Each experimental substrate sample was fabricated using greensheet technology on which a tungsten metallised heat resistor was formed. A kovar shell was attached to the back side of the substrate and filled with the low melting point alloy. The temperature distribution of the substrate was measured and it was confirmed that the substrate back surface temperature was fixed at the melting point for several minutes by thermal absorption while the alloy's phase changed. This new cooling technology is extremely useful for high-power circuit packages.

KEYWORDS: package cooling technology, multilayer ceramic substrate, chip junction temperature, low melting point alloy, thermal conductivity, heat of fusion, melting point, specific heat, thermal resistance, thermal capacitance
URL: http://jjap.ipap.jp/link?JJAP/29/1377/
DOI: 10.1143/JJAP.29.1377

References | Citing Article (1)

1. M. B. Shamash and S. G. Konosowski, Jr: Proc. 18th ECC, Washington, D. C., 1968 (The Institute of Electrical and Electronics Engineers, Inc., Washington, D.C., 1968) p. 350.
2. B. T. Clark and Y. M. Hill: IEEE Trans. CHMT, CHMT-3 (1980) 89.
3. M. G. Freedman and F. W. Short: Proc. Int. J. for Hybrid Microelectronics Vol. 4 No. 2 (International Society for Hybrid Microelectronics, Chicago, 1981) p. 51.
4. S. Oktay, R. Dessauer and J. L. Horvath: Proc. IEEE Int. Conf. on Computer Design, 1983 (IEEE, New York, 1983) p. 2.
5. S. Ogihara, T. Yasuda, K. Otsuka and F. Kobayashi: Proc. 3rd IMC, Tokyo, 1984 (ISHM Japan Chapter, Tokyo, 1984) p. 423.
6. R. C. Chu, U. P. Hwang and R. E. Simons: IBM J. Res. & Develop. 26 (1982) 45.
7. T. Watari and H. Murano: Proc. 35th ECC, Washington, D.C., 1985 (The Institute of Electrical and Electronics Engineering, Inc., Washington, D. C., 1985) p. 192.
8. H. Yamamoto, Y. Udagawa and T. Okada: FUJITSU S&T J. 37 (1986) No. 2, 124.
9. Y. Fukuoka and M. Ishizuka: Jpn. J. Appl. Phys. 28 (1989) 1578[IPAP].
10. T. D. Slagh and H. T. Nagle: Proc. Int. Microelectronics Symp. Vancouver, B. C., 1976 (International Society for Hybrid Microelectronics, Alabama, 1976) p. 19.