Jpn. J. Appl. Phys. 42 (2003) pp. 2429-2433  |Next Article|  |Table of Contents|
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Threshold Voltage of Si Single-Electron Transistor

Akira Fujiwara, Seiji Horiguchi, Masao Nagase and Yasuo Takahashi

(Received September 17, 2002; accepted for publication October 28, 2002)

We experimentally evaluate threshold voltages of Si single-electron transistors (SET) in order to investigate the effect of offset charges. Threshold voltages show a clear relation to the gate capacitance of SETs, which is a device parameter reflecting the size of the Si island of SETs. This indicates that the fabricated Si SETs do not suffer much from random offset charges that cause the threshold voltages to fluctuate. Moreover, our theoretical analysis shows that the obtained negative threshold voltages strongly suggest the reduction of the band gap of Si islands due to oxidation-induced strain.

KEYWORDS: silicon, single-electron transistor (SET), threshold voltage, offset charge, background charge, pattern-dependent oxidation, strain
URL: http://jjap.ipap.jp/link?JJAP/42/2429/
DOI: 10.1143/JJAP.42.2429

References | Citing Articles (8)

1. Y. Takahashi, Y. Ono, A. Fujiwara and H. Inokawa: J. Phys.: Condens. Matter 14 (2002) R995[IoP STACKS].
2. Y. Takahashi, M. Nagase, H. Namatsu, K. Kurihara, K. Iwadate, Y. Nakajima, S. Horiguchi, K. Murase and M. Tabe: Electron. Lett. 31 (1995) 136[AIP Scitation].
3. Y. Takahashi, H. Namatsu, K. Kurihara, K. Iwadate, M. Nagase and K. Murase: IEEE Trans. Electron Devices 43 (1996) 1213[CrossRef].
4. D. H. Kim, S. K. Sung, K. R. Kim, J. D. Lee, B. G. Park, B. H. Choi, S. W. Hwang and D. Ahn: IEEE Trans. Electron Devices 49 (2002) 627[CrossRef].
5. K. K. Likharev: Proc. IEEE 87 (1999) 606.
6. S. Horiguch, M. Nagase, K. Shiraishi, H. Kageshima, Y. Takahashi and K. Murase: Jpn. J. Appl. Phys. 40 (2001) L29[IPAP].
7. A. Fujiwara, Y. Takahashi, H. Namatsu, K. Kurihara and K. Murase: Jpn. J. Appl. Phys. 37 (1998) 3257[IPAP].
8. M. Nagase, A. Fujiwara, K. Yamazaki Y. Takahashi, K. Murase and K. Kurihara: Microelectron. Eng. 41/42 (1998) 527.
9. M. Nagase and K. Kurihara: Microelectron. Eng. 53 (2000) 257.
10. M. Nagase, S. Horiguchi, A. Fujiwara Y. Ono, K. Yamazaki, H. Namatsu and Y. Takahashi: Appl. Surf. Sci. 190 (2002) 144[CrossRef].
11. M. Nagase, S. Horiguchi, A. Fujiwara and Y. Takahashi: Ext. Abstr. 2002 Int. Conf. Solid State Devices and Materials (Business Center for Academic Societies Japan, Tokyo, 2002) p. 552.
12. M. Nagase, S. Horiguchi, A. Fujiwara and Y. Takahashi: Ext. Abstr. 2001 Int. Conf. Solid State Devices and Materials (Business Center for Academic Societies Japan, Tokyo, 2001) p. 436.
13. W. H. Huber, S. B. Martin and N. M. Zimmerman: Experimental Implementation Quantum Computation (IQC'01) (Princeton, NJ, Rinton Press) p. 176.
14. N. M. Zimmerman, W. H. Huber, A. Fujiwara and Y. Takahashi: Appl. Phys. Lett. 79 (2001) 3188[AIP Scitation].
15. A. A. M. Staring, H. van Houten, C. W. J. Beenakker and C. T. Foxon: High Magnetic Fields in Semiconductor Physics III, ed. G. Landwehr (Springer, Berlin, 1992) p. 301.
16. Y. Omura, S. Horiguchi, M. Tabe and K. Ishii: IEEE Electron Device Lett. 14 (1993) 569[CrossRef].