Jpn. J. Appl. Phys. 45 (2006) pp. L807-L809  |Previous Article| |Next Article|  |Table of Contents|
|Full Text PDF (146K)| |Buy This Article|

Letter

Nano-Scale Memory Characteristics of Silicon Nitride Charge Trapping Layer with Silicon Nanocrystals

Hyejung Choi, Sangmoo Choi1, Tae-Wook Kim, Takhee Lee and Hyunsang Hwang

Department of Materials Science and Engineering, Gwangju Institute of Science and Technology, #1 Oryong-dong, Buk-gu, Gwangju 500-712, Korea
1SDL, Samsung Advanced Institute of Technology, Suwon 446-712, Korea

(Received February 15, 2006; accepted June 27, 2006; published online July 28, 2006)

Silicon nanocrystals (Si-NCs) embedded in a silicon nitride (SiN) layer were fabricated as a charge trapping layer for nonvolatile memory (NVM) device applications. Nano-scale memory characteristics were investigated using conductive atomic force microscopy (C-AFM) and a semiconductor parameter analyzer. Nano-scale memory characteristics of Si-NCs embedded in the SiN layer were obtained from the shift of the current–voltage (IV) curve. Charge trapping/detrapping and multi-level charge storage in Si-NCs embedded in the SiN layer were obtained at a metal–oxide–semiconductor (MOS) structure of about 100 nm2 at room temperature. The flat band voltage (VFB) shift was about 0.37 V, which is agreed well with the calculated VFB shift for one electron per nanocrystal.

KEYWORDS: SONOS, nonvolatile memory, C-AFM, Si nanocrystal, nano-scale memory
URL: http://jjap.ipap.jp/link?JJAP/45/L807/
DOI: 10.1143/JJAP.45.L807


|Full Text PDF (146K)| |Buy This Article| Citation:


References | Citing Articles (2)

  1. B. Eitan, P. Pavan, I. Bloom, E. Aloni, A. Frommer and D. Finzi: IEEE Electron Device Lett. 21 (2000) 543[CrossRef].
  2. M. L. French, C. Y. Chen, H. Sathianathan and M. H. White: IEEE Trans. Compon., Packag., Manuf. Technol. 17 (1994) 390.
  3. M. K. Cho and D. M. Kim: IEEE Electron Device Lett. 21 (2000) 399[CrossRef].
  4. L. Guo, E. Leobandung and S. Y. Chou: Science 275 (1997) 649[Science].
  5. I. Kim, S. Han, K. Han, J. Lee and H. Shin: Jpn. J. Appl. Phys. 40 (2001) 447[IPAP].
  6. S. Tiwari, F. Rana, H. Hanafi, A. Hartstein, F. C. Emmanuel and K. Chan: Appl. Phys. Lett. 68 (1996) 1377[AIP Scitation].
  7. S. Choi, H. Yang, M. Chang, S. Baek, H. Hwang, S. Jeon, J. Kim and C. Kim: Appl. Phys. Lett. 86 (2005) 251901[AIP Scitation].
  8. A. Olbrich, B. Ebersberger and C. Boit: Appl. Phys. Lett. 73 (1998) 3114[AIP Scitation].
  9. S. Zaima, A. Seko, Y. Watanabe, T. Sago, M. Sakashita, H. Kondo, A. Sakai and M. Ogawa: Ext. Abstr. 2005 Int. Conf. Solid State Devices and Materials, 2005, p. 236.
  10. M. Porti, M. Avidano, M. Nafria, X. Aymerich, J. Carreras and B. Garrido: J. Appl. Phys. 98 (2005) 056101[AIP Scitation].
  11. X. Blasco, M. Nafria and X. Aymerich: Rev. Sci. Instrum. 76 (2005) 016105[AIP Scitation].
  12. B. G. Streetman and S. Banerjee: Solid State Electronic Devices (Prentice Hall) 5th ed., p. 286.

|TOP|  |Previous Article| |Next Article|  |Table of Contents| |JJAP Home|
Copyright © 2010 The Japan Society of Applied Physics
Contact Information